1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a technology which corrects a difference between a model delay value of a delay locked loop (DLL) and an actual delay value.
2. Related Art
A semiconductor apparatus operates in synchronization with a reference periodic pulse signal, such as a clock signal, in order to improve an operation speed and to effectively perform an internal operation. Therefore, most semiconductor apparatuses operate using a clock signal supplied from outside or an internal clock signal generated depending on the particular necessity and/or configuration.
Meanwhile, an input clock signal applied to a semiconductor apparatus is delayed internally in the semiconductor apparatus. Therefore, when data is outputted by using the delayed clock signal, the outputted data may not be synchronized with the input clock signal. Accordingly, the semiconductor apparatus compensates for a phase difference between the input clock signal and the internal clock signal using a delayed lock loop (DLL), a phase locked loop (PLL) and soon.
FIG. 1 is a configuration diagram of a conventional semiconductor apparatus.
Referring to FIG. 1, the conventional semiconductor apparatus may include a DLL 2 which includes an internal clock path composed of a plurality of repeaters 3 and 5, a transfer line 4, and an output driving unit 6.
The DLL 2 is configured to output a DLL clock signal DLL_CLK of which the phase is controlled by reflecting a delay value of the internal clock path into an applied input clock signal EXT_CLK. Since the internal clock path has a delay value of ‘tDO’, the DLL 2 advances the phase of the input clock signal EXT_CLK by a delay value of ‘-tDO’ to generate the DLL clock signal DLL_CLK. Therefore, an output clock signal STB_CLK which is finally outputted through the internal clock path has the same phase as the input clock signal EXT_CLK.
Meanwhile, the DLL 2 may include a delay model unit (not shown) in which the delay value of the internal clock path is modeled. The delay model unit is designed in such a manner as to have substantially the same delay value as that of the internal clock path in the ideal case. In the delay model unit in which the components of the internal clock path are modeled, however, the positions of the components are different from those of actual components. Between the model delay value and the delay value of each component, a difference may occur. In particular, the difference may further increase due to changes in process and voltage. Such a difference between the delay values may cause a reduction in timing margin of an internal circuit which operates using the DLL clock signal DLL_CLK. Therefore, there is demand for a technology capable of solving such a problem.